Many ICs have a power down mode that is used to save power and, in the case of battery powered environments, extend the battery life of the system.
The transition from the power down mode to the normal mode is usually controlled by an external interrupt signal or is pre-programmed at fixed intervals. The latter case is most common in sand alone systems where an IC must “wake up” at predetermined intervals to perform functions such as monitor sensors or communicate with other devices, for example.
When an IC is required to wake-up at known intervals, some circuitry is required to be operating even during the power down mode to keep track of time and to wake the IC up. This circuitry usually includes an oscillator that is sufficiently precise and a real time counter. The oscillator is often a crystal oscillator since it is very precise and is not sensible to environmental variations such as temperature and input voltage variations. A drawback of using a crystal oscillator is that it requires a relatively large biais current (in the order of tens of μA) during the power down mode.
To overcome this drawback, Chapman et al. in their U.S. Pat. No. 5,845,204 issued on Dec. 1, 1998 and entitled “Method and apparatus for controlling the wakeup logic of a radio receiver in sleep mode” suggested the use of two oscillators. A crystal oscillator for its precision and a low power ring oscillator that runs in the sleep mode. During the wakeup time, the low power ring oscillator is calibrated to compensate for its inaccuracy. While Chapman's method and apparatus is an improvement over apparatuses using crystal oscillator during the sleep mode, it still has drawbacks related to the compensation of the ring oscillator frequency.